Charge release circuit, display substrate, display device and charge release method thereof

ABSTRACT

A charge release circuit, a display substrate, a display device and a charge release method thereof are provided. The charge release circuit including: a controller, a charge release sub-circuit and a first conductor, wherein the charge release sub-circuit is respectively connected with the controller, the first conductor and a second conductor in an active area of an array substrate, and the charge release sub-circuit is configured to conduct the first conductor and the second conductor under a control of the controller, so as to allow charges on the second conductor to move to the first conductor. The charge release circuit can solve the problem that the display panel in the black-screen state displays bright spots so as to reduce the number of bright spots on the display panel in the black-screen state.

The application claims priority to the Chinese patent application No.201720002380.1, filed on Jan. 3, 2017, the entire disclosure of which isincorporated herein by reference as part of the present application.

TECHNICAL FIELD

Examples of the present disclosure relate to a charge release circuit, adisplay substrate, a display device and a charge release method thereof.

BACKGROUND

A liquid crystal display (LCD) includes a color filter (CF) substrate,an array substrate, and liquid crystals disposed between the CFsubstrate and the array substrate, the color filter (CF) substrate andthe array substrate are oppositely arranged.

For instance, a common electrode is formed on a base substrate of the CFsubstrate, a plurality of transversely arranged gate lines and aplurality of longitudinally arranged data lines are formed on a basesubstrate of the array substrate, the gate lines and the data lines areintersected with each other to form a plurality of pixel regions, and athin-film transistor (TFT) and a pixel electrode are formed in each ofthe plurality of pixel regions. For instance, the TFT includes a gateelectrode connected with the gate line, a source electrode connectedwith the data line, and a drain electrode connected with the pixelelectrode. When a display panel is controlled to display an image, theTFT can be switched on by applying a voltage to the gate electrodethrough the gate line, a pixel voltage is applied to the pixel electrodethrough the data line, the source electrode and the drain electrode, anda common voltage is applied to the common electrode. The liquid crystalsare rotated under an action of the pixel voltage and the common voltage,so that the display panel can display the image. When the display panelis not required to be controlled to display the image, the liquidcrystals are not rotated by stopping applying voltages to the pixelelectrode and the common electrode, so that the display panel can be ina black-screen state.

SUMMARY

Examples of the present disclosure provide a charge release circuit, adisplay substrate, a display device and a charge release method thereof.

At least one example of the present disclosure provides a charge releasecircuit, comprising: a controller, a charge release sub-circuit and afirst conductor, wherein the charge release sub-circuit is respectivelyconnected with the controller, the first conductor and a secondconductor in an active area of an array substrate, and the chargerelease sub-circuit is configured to conduct the first conductor and thesecond conductor under a control of the controller, so as to allowcharges on the second conductor to move to the first conductor.

According to the charge release circuit provided by an example of thepresent disclosure, the second conductor comprises at least one gateline, the controller comprises a first control line, and the chargerelease sub-circuit comprises a first charge release unit, and whereinthe first charge release unit is respectively connected with the atleast one gate line, the first control line and the first conductor, andthe first charge release unit is configured to conduct the firstconductor and the at least one gate line according to a control signalon the first control line.

According to the charge release circuit provided by an example of thepresent disclosure, the second conductor comprises a plurality of gatelines, the first charge release unit comprises a plurality of firsttransistors, the first control line is perpendicular to the gate line,and the plurality of first transistors are in a one-to-onecorrespondence with the plurality of gate lines; a gate electrode ofeach of the plurality of first transistors is connected with the firstcontrol line, a first electrode of each of the plurality of firsttransistors is connected with one gate line in the plurality of gatelines, and a second electrode of each of the plurality of firsttransistors is connected with the first conductor.

According to the charge release circuit provided by an example of thepresent disclosure, the second conductor comprises at least one dataline, the controller comprises a second control line, and the chargerelease sub-circuit comprises a second charge release unit; and thesecond charge release unit is respectively connected with the at leastone data line, the second control line and the first conductor, and thesecond charge release unit is configured to conduct the first conductorand the at least one data line according to a control signal on thesecond control line.

According to the charge release circuit provided by an example of thepresent disclosure, the second conductor comprises a plurality of datalines, the second charge release unit comprises a plurality of secondtransistors, the second control line is perpendicular to the data line,and the plurality of second transistors are in a one-to-onecorrespondence with the plurality of data lines; and a gate electrode ofeach of the plurality of second transistors is connected with the secondcontrol line, a first electrode of each of the plurality of secondtransistors is connected with one data line in the plurality of datalines, and a second electrode of each of the plurality of secondtransistors is connected with the first conductor.

According to the charge release circuit provided by an example of thepresent disclosure, the second conductor further comprises at least onepixel electrode, the controller further comprises a third control line,and the charge release sub-circuit further comprises a third chargerelease unit, and the third charge release unit is respectivelyconnected with the gate line and the third control line in the arraysubstrate, and the third charge release unit is configured to write acontrol signal on the third control line into the gate line so as toconduct each pixel electrode and the data line connected with the pixelelectrode.

According to the charge release circuit provided by an example of thepresent disclosure, the third charge release unit comprises a pluralityof third transistors, the plurality of third transistors are in aone-to-one correspondence with the plurality of gate lines in the arraysubstrate, and the second conductor comprises a plurality of pixelelectrodes connected with each gate line, and the third control line isperpendicular to the gate line, and both a gate electrode and a firstelectrode of each of the plurality of third transistors are connectedwith the third control line, and a second electrode of each of theplurality of third transistors is connected with one gate line in theplurality of gate lines.

According to the charge release circuit provided by an example of thepresent disclosure, a volume of the first conductor is greater than thatof the second conductor.

According to the charge release circuit provided by an example of thepresent disclosure, the first conductor is a common electrode line or astorage electrode line.

At least one example of the present disclosure provides a displaysubstrate, comprising any of the charge release circuits describedabove.

At least one example of the present disclosure provides a displaydevice, comprising a display panel, wherein the display panel comprisesany of the display substrates described above.

At least one example of the present disclosure provides a charge releasemethod of the display device according to claim 11, comprising: applyinga control signal to the controller when the display panel is in ablack-screen state, conducting the first conductor and the secondconductor under the control of the controller, and allowing charges onthe second conductor to move to the first conductor.

According to the method provided by an example of the presentdisclosure, the first conductor is a common electrode line or a storageelectrode line, and the second conductor is at least one of a gate line,a data line or a pixel electrode.

According to the charge release circuit provided by an example of thepresent disclosure, a volume of the first conductor is greater than thatof the second conductor.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly illustrate the technical solution of the examples ofthe disclosure, the drawings of the examples will be briefly describedin the following; it is obvious that the described drawings are onlyrelated to some examples of the disclosure. Those skilled in the art canalso obtain other drawings based on these drawings without any creativework.

FIG. 1 is a schematic diagram of a structure illustrating a chargerelease circuit provided by an example of the present disclosure;

FIG. 2A is a schematic view illustrating a structure of an arraysubstrate;

FIG. 2B is a schematic view illustrating a structure of another arraysubstrate;

FIG. 3 is a schematic view illustrating a structure of another chargerelease circuit provided by an example of the present disclosure;

FIG. 4 is a schematic view illustrating a structure of still anothercharge release circuit provided by an example of the present disclosure;

FIG. 5 is a schematic view illustrating a structure of still anothercharge release circuit provided by an example of the present disclosure;

FIG. 6 is a schematic view illustrating a structure of a charge releasecircuit provided by another example of the present disclosure; and

FIG. 7 is a schematic view illustrating a structure of another chargerelease circuit provided by another example of the present disclosure.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of theexamples of the disclosure apparent, the technical solutions of theexamples will be described in a clearly and fully understandable way inconnection with the drawings related to the examples of the disclosure.Apparently, the described examples are just a part but not all of theexamples of the disclosure. Based on the described examples herein,those skilled in the art can obtain other example(s), without anyinventive work, which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms usedherein have the same meanings as commonly understood by one of ordinaryskill in the art to which the present disclosure belongs. The terms“first,” “second,” etc., which are used in the present disclosure, arenot intended to indicate any sequence, amount or importance, butdistinguish various components. Also, the terms such as “a,” “an,” etc.,are not intended to limit the amount, but indicate the existence of atleast one. The terms “comprise,” “comprising,” “include,” “including,”etc., are intended to specify that the elements or the objects statedbefore these terms encompass the elements or the objects and equivalentsthereof listed after these terms, but do not preclude the other elementsor objects. The phrases “connect”, “connected”, etc., are not intendedto define a physical connection or mechanical connection, but mayinclude an electrical connection, directly or indirectly. “On,” “under,”“right,” “left” and the like are only used to indicate relative positionrelationship, and when the position of the object which is described ischanged, the relative position relationship may be changed accordingly.

When a display panel is not required to be controlled to display animage, as some charges will be left on partial conductors (e.g., gatelines and data lines) in an active area of an array substrate whenvoltage is applied at the previous moment, partial liquid crystals willstill be rotated, so the display panel in a black-screen state willdisplay bright spots.

Transistors adopted in all the examples of the present disclosure can beall TFTs, field effect transistors (FETs) or other elements with samecharacteristics. In view of the function in a circuit, the transistorsadopted in the examples of the present disclosure are mainly switchingtransistors. As a source electrode and a drain electrode of theswitching transistor adopted herein are symmetrical, the sourceelectrode and the drain electrode can be exchanged. In the examples ofthe present disclosure, in order to distinguish two electrodes of thetransistor except a gate electrode, the source electrode is referred toas first electrode and the drain electrode is referred to as secondelectrode. According to the form in the figure, the gate electrode isdisposed in the middle of the transistor, the source electrode isdisposed at a signal input end, and the drain electrode is disposed at asignal output end. In addition, the switching transistor adopted in theexamples of the present disclosure includes at least one of a P-typeswitching transistor or an N-type switching transistor. The P-typeswitching transistor is switched on when the gate electrode is in a lowlevel and switched off when the gate electrode is in a high level. TheN-type switching transistor is switched on when the gate electrode is ina high level and switched off when the gate electrode is in a low level.

FIG. 1 is a schematic view illustrating a structure of a charge releasecircuit 0 provided by an example of the present disclosure. Asillustrated in FIG. 1, the charge release circuit 0 can include: acontroller 01, a charge release sub-circuit 02 and a first conductor 03.The charge release sub-circuit 02 is respectively connected with thecontroller 01, the first conductor 03 and a second conductor A in anactive area of an array substrate. The controller 01 can be a controlmodule. The charge release sub-circuit 02 can be a charge releasemodule.

The charge release sub-circuit 02 is configured to conduct the firstconductor 03 and the second conductor A under a control of thecontroller 01 to allow charges on the second conductor A to move to thefirst conductor 03. For instance, the first conductor 03 can begrounded.

For instance, in the charge release circuit provided by the example ofthe present disclosure, the charge release sub-circuit 02 isrespectively connected with the controller 01 and the first conductor03, and the charge release sub-circuit 02 is configured to conduct thefirst conductor 03 and the second conductor A in an active area of thearray substrate under the function of the controller 01, so that thecharge on the second conductor A can be moved to the first conductor 03,thereby reducing the quantity of the charges on the second conductor Ain the active area of the array substrate, so as to reduce the rotationprobability of liquid crystals when the display panel is in ablack-screen state, and reduce the number of bright spots on the displaypanel in the black-screen state.

FIG. 2A is a schematic view illustrating a structure of an arraysubstrate 1. As illustrated in FIG. 2A, the array substrate 1 caninclude a base substrate 100, a plurality of gate lines A1 and aplurality of data lines A2 are formed in an active area Y of the basesubstrate 100 and are insulated from each other and intersected witheach other to form a plurality of pixel regions. A transistor A4 and apixel electrode A3 are formed in each of the plurality of pixel regions,a gate electrode of the transistor A4 is connected with the gate line A1through which the pixel region is formed, a source electrode of thetransistor A4 is connected with the data line A2 through which the pixelregion is formed, and a drain electrode of the transistor A4 isconnected with a pixel electrode A3 in the pixel region. For instance, afirst common electrode line 031 and a second common electrode line 032are formed in a non-active area (namely an edge area) of the basesubstrate 100. For instance, the first common electrode line 031 isperpendicular to the gate line A1, and the second common electrode line032 is perpendicular to the data line A2. For instance, the first commonelectrode line 031 is insulated from the gate line A1, and the secondcommon electrode line 032 is insulated from the data line A2. Forinstance, the data line is configured to input a data signal into apixel, and the data signal, for instance, includes a grayscale voltage.For instance, the gate line is configured to input a gate signal intothe transistor, and the gate signal, for instance, includes a gatevoltage.

As illustrated in FIG. 2B, a plurality of storage electrode lines A0 canfurther be formed in the active area Y of the base substrate 100, andeach of the plurality of storage electrode lines A0 can run through arow of pixel regions and is parallel with the gate line A1.

For instance, as illustrated in FIGS. 2A and 2B, the transistors A4 arearranged in an array, each of the plurality of gate lines is connectedwith a row of transistors A4, each of the plurality of the data line isconnected with a column of transistors A4, and each pixel electrode isconnected with a transistor A4. The pixel electrode corresponding toeach gate line is: a pixel electrode connected with the gate linethrough the transistor A4. The data line corresponding to each pixelelectrode is: a data line connected with the pixel electrode through thetransistor A4.

For instance, a volume of the first conductor 03 can be greater thanthat of the second conductor A. At this point, as the volume of thefirst conductor 03 is large, the quantity of charges that can be carriedby the first conductor 03 is also large, so the first conductor 03 cancarry more charges for the second conductor A. For instance, a linewidth of the first conductor 03 can be greater than that of the secondconductor A, so the quantity of charges that can be carried by the firstconductor 03 is large. Illustratively, the array substrate can include abase substrate, and multiple wires can be formed on the base substrate,a common electrode line and a storage electrode line are wide and otherwires (e.g., gate line and data line) are narrow, the first conductor 03can be the common electrode line or the storage electrode line on thearray substrate, and the second conductor A can be any conductor in theactive area of the array substrate, for instance, the second conductor Acan be a gate line, a data line or a pixel electrode.

Description will be given below to the charge release circuit providedby the examples of the present disclosure by taking the case that thefirst conductor is the common electrode line on the array substrate andthe second conductor is respectively the gate line, the data line or thepixel electrode on the array substrate as an example.

In the first aspect, the second conductor can include at least one gateline, the controller can include a first control line, the chargerelease sub-circuit can include a first charge release unit, and thefirst charge release unit is respectively connected with the at leastone gate line, the first control line and the first conductor, and thefirst charge release unit is configured to conduct the first conductorand the at least one gate line according to a control signal on thefirst control line.

FIG. 3 is a schematic view illustrating a structure of a charge releasecircuit 0 provided by an example of the present disclosure. Asillustrated in FIG. 3, the second conductor can include a plurality ofgate lines A1, a first charge release unit 021 can include a pluralityof first transistors 0211, and the plurality of first transistors 0211are in a one-to-one correspondence with the plurality of gate lines A1.A gate electrode G of each of the plurality of first transistors 0211 isconnected with a first control line 011, a first electrode J1 of each ofthe plurality of first transistors 0211 is connected with the gate lineA1 corresponding to the first transistor, a second electrode J2 of eachof the plurality of first transistors 0211 is connected with a firstcommon electrode line 031 perpendicular to the gate line A1, and thefirst control line 011 is perpendicular to the gate line A1. Forinstance, the first control line 011 is insulated from the gate line A1.

When a display panel is required to be controlled to be in ablack-screen state, a control signal can be inputted into the firstcontrol line 011, so that each of the plurality of first transistors0211 in the plurality of first transistors 0211 can be in an on state(namely the first electrode J1 and the second electrode J2 of each ofthe plurality of first transistors 0211 are in the on state), and theneach of the plurality of first transistors 0211 conducts the gate lineA1 and the first common electrode line 031 which are connected by thefirst transistor. At this point, if there are residual charges on thegate line A1, the residual charges can flow towards the first commonelectrode line 031, so the quantity of charges on the gate line A1 canbe reduced. At this point, the first conductor for carrying the chargeson the second conductor is the first common electrode line 031. Afterthe display panel is in the black-screen state, the quantity of chargeson the gate line is small, thereby preventing liquid crystals from beingrotated under an action of voltage, so as to avoid bright spots to bedisplayed on the display panel, and solve the problem of bright spotsbeing displayed by the display panel in the black-screen state.

In the second aspect, the second conductor can include at least one dataline, the controller can include a second control line, the chargerelease sub-circuit can include a second charge release unit, and thesecond charge release unit can be respectively connected with the atleast one data line, the second control line and the first conductor,and the second charge release unit is configured to conduct the firstconductor and the at least one data line according to a control signalon the second control line.

FIG. 4 is a schematic view illustrating a structure of still anothercharge release circuit 0 provided by an example of the presentdisclosure. As illustrated in FIG. 4, the at least one data line in asecond conductor can include a plurality of data lines A2, a secondcharge release unit 022 can include a plurality of second transistors0221, and the plurality of second transistors 0221 can be in aone-to-one correspondence with the plurality of data lines A2. A gateelectrode G of each of the plurality of second transistors 0221 isconnected with the second control line 012, a first electrode J1 of eachof the plurality of second transistors 0221 is connected with the dataline A2 corresponding to the second transistor, and a second electrodeJ2 of each of the plurality of second transistors 0221 is connected witha second common electrode line 032 perpendicular to the data line A2.For instance, the second control line 012 can be perpendicular to thedata line A2.

When the display panel is required to be controlled to be in ablack-screen state, a control signal can be inputted into the secondcontrol line 012, so that each of the plurality of second transistors0221 can be in an on state so as to conduct the data line A2 and thesecond common electrode line 032 which are connected by the secondtransistor. At this point, if there are residual charges on the dataline A2, the residual charges can flow towards the second commonelectrode line 032, so the quantity of charges on the data line A2 canbe reduced. At this point, the first conductor for carrying the chargeson the second conductor is the second common electrode line 032. Afterthe display panel is in a black-screen state, the quantity of charges onthe data line is small, thereby preventing liquid crystals from beingrotated under an action of voltage so as to avoid bright spots to bedisplayed on the display panel.

In the third aspect, on the basis of the second aspect, the secondconductor can further include at least one pixel electrode, thecontroller can further include a third control line, the charge releasesub-circuit can further include a third charge release unit, and thethird charge release unit can be respectively connected with the gateline and the third control line in the array substrate, and the thirdcharge release unit is configured to write a control signal on the thirdcontrol line into the gate line so as to conduct the pixel electrode andthe data line corresponding to the pixel electrode.

FIG. 5 is a schematic view illustrating a structure of still anothercharge release circuit 0 provided by an example of the presentdisclosure. As illustrated in FIG. 5, on the basis of FIG. 4, the chargerelease sub-circuit can further include a third charge release unit 023,the third charge release unit 023 can include a plurality of thirdtransistors 0231 which are in a one-to-one correspondence with theplurality of gate lines A1 in the array substrate, at least one pixelelectrode in a second conductor can include a plurality of pixelelectrodes A3 corresponding to each gate line A1, both a gate electrodeG and a first electrode J1 of each of the plurality of third transistors0231 are connected with a third control line 013, a second electrode J2of each of the plurality of third transistors 0231 is connected with thegate line A1 corresponding to the third transistor 0231, and the thirdcontrol line 013 can be perpendicular to the gate line A1.

When the display panel is required to be controlled to be in ablack-screen state, a control signal can also be inputted into the thirdcontrol line 013, so that each of the plurality of third transistors0231 can be in an on state. Thus, the control signal on the thirdcontrol line 013 can be inputted into the gate line A1 corresponding tothe third transistor 0231 along the first electrode and the secondelectrode of the third transistor 0231, and the transistors in the pixelregions connected with the gate line A1 are switched on, and hence thepixel electrode A3 corresponding to the gate line A1 and the data lineA2 corresponding to the pixel electrode A3 can be conducted with eachother. For instance, a control signal can also be inputted into thesecond control line 012, so that each of the plurality of secondtransistors 0221 can be in an on state so as to conduct the data line A2and the second common electrode line 032 which are connected by thesecond transistor. At this point, if there are residual charges on thepixel electrode A3, the residual charges can flow towards the data lineA2 and then flow towards the second common electrode line 032, so thequantity of charges on the data line A2 and the pixel electrode A3 canbe reduced. At this point, the first conductor for carrying the chargeson the second conductor is the second common electrode line 032. Afterthe display panel is in a black-screen state, the quantity of charges onthe data line and the pixel electrode is small, thereby preventingliquid crystals from being rotated under an action of voltage so as toavoid bright spots to be displayed on the display panel.

In the fourth aspect, FIG. 6 is a schematic view illustrating astructure of a charge release circuit 0 provided by another example ofthe present disclosure. As illustrated in FIG. 6, a second conductorincludes a plurality of gate lines A1 and a plurality of data lines A2on an array substrate, and the charge release circuit 0 can include aplurality of first transistors 0211, a plurality of second transistors0221, a first control line 011, a second control line 012, a firstcommon electrode line 031 and a second common electrode line 032.

For instance, the first common electrode line 031 is perpendicular tothe gate line A1 and parallel with the data line A2, the first controlline 011 is parallel with the first common electrode line 031, thesecond common electrode line 032 is perpendicular to the data line A2and parallel with the gate line A1, the second control line 012 isparallel with the second common electrode line 032, the plurality offirst transistors 0211 are in a one-to-one correspondence with theplurality of gate lines A1, and the plurality of second transistors 0221are in a one-to-one correspondence with the plurality of data lines A2.A gate electrode of each of the plurality of first transistors 0211 isconnected with the first control line 011, a first electrode of each ofthe plurality of first transistors 0211 is connected with the gate lineA1 corresponding to the first transistor, and a second electrode of eachof the plurality of first transistors 0211 is connected with the firstcommon electrode line 031. A gate electrode of each of the plurality ofsecond transistors 0221 is connected with the second control line 012, afirst electrode of each of the plurality of second transistors 0221 isconnected with the data line A2 corresponding to the second transistor,and a second electrode of each of the plurality of second transistors0221 is connected with the second common electrode line 032.

When the display panel is required to be controlled to be in ablack-screen state, a control signal can be inputted into the firstcontrol line 011, so that each of the plurality of first transistors0211 can be in an on state so as to conduct the gate line A1 and thefirst common electrode line 031 which are connected by the firsttransistor. At this point, if there are residual charges on the gateline A1, the residual charges can flow towards the first commonelectrode line 031, so the quantity of charges on the gate line A1 canbe reduced. A control signal can also be inputted into the secondcontrol line 012, so that each of the plurality of second transistors0221 can be in an on state so as to conduct the data line A2 and thesecond common electrode line 032 which are connected by the secondtransistor. At this point, if there are residual charges on the dataline A2, the residual charges can flow towards the second commonelectrode line 032, so the quantity of charges on the data line A2 canbe reduced. At this point, the first conductor for carrying the chargeson the second conductor is the first common electrode line 031 and thesecond common electrode line 032. After the display panel is in ablack-screen state, the quantity of charges on the data line is small.

In the fifth aspect, FIG. 7 is a schematic view illustrating a structureof another charge release circuit 0 provided by another example of thepresent disclosure. As illustrated in FIG. 7, the second conductorincludes a plurality of gate lines A1, a plurality of data lines A2 anda plurality of pixel electrodes A3 on the array substrate, and thecharge release circuit 0 can include a plurality of first transistors0211, a plurality of second transistors 0221, a plurality of thirdtransistors 0231, a first control line 011, a second control line 012, athird control line 013, a first common electrode line 031 and a secondcommon electrode line 032.

For instance, the first common electrode line 031 is perpendicular tothe gate line A1 and parallel with the data line A2, both the firstcontrol line 011 and the third control line 013 are parallel with thefirst common electrode line 031 and disposed near the first commonelectrode line 031. For instance, the first control line 011 is disposedon a side of the first common electrode line 031 close to the activearea, and the third control line 013 is disposed on a side of the firstcommon electrode line 031 far away from the active area. The secondcommon electrode line 032 is perpendicular to the data line A2 andparallel with the gate line A1. The second control line 012 is parallelwith the second common electrode line 032 and disposed near the secondcommon electrode line 032, for instance, disposed on a side of thesecond common electrode line 032 close to the active area.

The plurality of first transistors 0211 are in a one-to-onecorrespondence with the plurality of gate lines A1, the plurality ofsecond transistors 0221 are in a one-to-one correspondence with theplurality of data lines A2, and the plurality of third transistors 0231are in a one-to-one correspondence with the plurality of gate lines A1.A gate electrode of each of the plurality of first transistors 0211 isconnected with the first control line 011, a first electrode of each ofthe plurality of first transistors 0211 is connected with the gate lineA1 corresponding to the first transistor, and a second electrode of eachof the plurality of first transistors 0211 is connected with the firstcommon electrode line 031. A gate electrode of each of the plurality ofsecond transistors 0221 is connected with the second control line 012, afirst electrode of each of the plurality of second transistors 0221 isconnected with the data line A2 corresponding to the second transistor,and a second electrode of each of the plurality of second transistors0221 is connected with the second common electrode line 032. Both a gateelectrode and a first electrode of each of the plurality of thirdtransistors 0231 is connected with the third control line 013, and asecond electrode of each of the plurality of third transistors 0231 isconnected with the gate line A1 corresponding to the third transistor.

When the display panel is required to be controlled to be in ablack-screen state, a control signal can be inputted into the firstcontrol line 011, so that each of the plurality of first transistors0211 can be in an on state so as to conduct the gate line A1 and thefirst common electrode line 031 which are connected by the firsttransistor. At this point, if there are residual charges on the gateline A1, the residual charges can flow towards the first commonelectrode line 031, so the quantity of charges on the gate line A1 canbe reduced.

For instance, a control signal can also be inputted into the secondcontrol line 012, so that each of the plurality of second transistors0221 can be in an on state so as to conduct the data line A2 and thesecond common electrode line 032 which are connected by the secondtransistor. At this point, if there are residual charges on the dataline A2, the residual charges can flow towards the second commonelectrode line 032, so the quantity of charges on the data line A2 canbe reduced. After the display panel is in a black-screen state, thequantity of charges on the data line is small.

Moreover, a control signal can also be inputted into the third controlline 013, so that each of the plurality of third transistors 0231 can bein an on state. Thus, the control signal on the third control line 013can be inputted into the gate line A1 corresponding to the thirdtransistor 0231 along the first electrode and the second electrode ofthe third transistor 0231, and the pixel electrode A3 corresponding tothe gate line A1 and the data line A2 corresponding to the pixelelectrode A3 can be conducted with each other. At this point, if thereare residual charges on the pixel electrode A3, the residual charges canflow towards the data line A2 and then flow towards the second commonelectrode line 032, so the quantity of charges on the data line A2 andthe pixel electrode A3 can be reduced.

At this point, the first conductor for carrying the charges on thesecond conductor is the first common electrode line 031 and the secondcommon electrode line 032. After the display panel is in a black-screenstate, the quantity of charges on the conductor (e.g., the gate line,the data line and the pixel electrode) in the active area of the arraysubstrate is small, thereby preventing liquid crystals from beingrotated under an action of voltage so as to avoid bright spots to bedisplayed on the display panel.

For instance, in the example of the present disclosure, components withsame extension direction can be formed in the same layer. For instance,at least two of the data line A2, the first common electrode line 031,the first control line 011 and the third control line 013 can be formedin the same layer, for instance, located in a first layer. At least twoof the gate line A1, the second control line 012 and the second commonelectrode line 032 can be formed in the same layer, for instance,located in a second layer. For instance, an insulating layer can bedisposed between the first layer and the second layer, so that two linesare not electrically connected at an intersection.

For instance, in the examples of the present disclosure, two componentscan be connected with each other through a transistor. For instance,black dots in the figures can refer to electrical connection. Forinstance, in the accompanying drawings, two intersected lines areinsulated from each other at the intersection.

In summary, in the charge release circuit provided by an example of thepresent disclosure, the charge release sub-circuit is respectivelyconnected with the controller and the first conductor, and the chargerelease sub-circuit is configured to conduct the first conductor and thesecond conductor in an active area of the array substrate under anaction of the controller, so that the charges on the second conductorcan be moved to the first conductor, thereby reducing the quantity ofcharges on the second conductor in the active area of the arraysubstrate, so as to reduce the rotation probability of liquid crystalswhen the display panel is in the black-screen state, and reduce thenumber of bright spots on the display panel in the black-screen state.

The example of the present disclosure further provides a displaysubstrate, which can include any charge release circuit as illustratedin FIG. 1, FIG. 3, FIG. 4, FIG. 5, FIG. 6 or FIG. 7.

Moreover, an example of the present disclosure further provides adisplay panel, which can include a display substrate provided with anycharge release circuit as illustrated in FIG. 1, FIG. 3, FIG. 4, FIG. 5,FIG. 6 or FIG. 7. For instance, the display substrate can be an arraysubstrate. For instance, the display panel can further include anopposing substrate arranged opposite to the array substrate. Forinstance, the opposing substrate can be a CF substrate, but not limitedthereto. In actual application, the display substrate can also be anopposing substrate. No limitation will be given herein in the examplesof the present disclosure.

Moreover, an example of the present disclosure further provides adisplay device, which includes a display panel. A display substrate inthe display panel can include any charge release circuit as illustratedin FIG. 1, FIG. 3, FIG. 4, FIG. 5, FIG. 6 or FIG. 7. The display devicecan be any product or component with display function such as an LCDpanel, e-paper, an organic light-emitting diode (OLED) panel, anactive-matrix organic light-emitting diode (AMOLED) panel, a mobilephone, a tablet PC, a TV, a display, a notebook computer, a digitalpicture frame or a navigator.

At least an example of the present disclosure further provides a chargerelease method of the display device, which includes releasing chargesby utilization of any foregoing charge release circuit. The methodincludes: applying a control signal to the controller when the displaypanel is in a black-screen state, conducting the first conductor and thesecond conductor under a control of the controller, and allowing chargeson the second conductor to move to the first conductor.

For instance, when the display panel is in the black-screen state, thedisplay device is in a standby state.

What have been described above are only specific implementations of thepresent disclosure, the protection scope of the present disclosure isnot limited thereto. Any changes or substitutions easily occur to thoseskilled in the art within the technical scope of the present disclosureshould be covered in the protection scope of the present disclosure.Therefore, the protection scope of the present disclosure should bebased on the protection scope of the claims.

1. A charge release circuit, comprising: a controller, a charge releasesub-circuit and a first conductor, wherein the charge releasesub-circuit is respectively connected with the controller, the firstconductor and a second conductor in an active area of an arraysubstrate, and the charge release sub-circuit is configured to conductthe first conductor and the second conductor under a control of thecontroller, so as to allow charges on the second conductor to move tothe first conductor.
 2. The charge release circuit according to claim 1,wherein the second conductor comprises at least one gate line, thecontroller comprises a first control line, and the charge releasesub-circuit comprises a first charge release unit, and wherein the firstcharge release unit is respectively connected with the at least one gateline, the first control line and the first conductor, and the firstcharge release unit is configured to conduct the first conductor and theat least one gate line according to a control signal on the firstcontrol line.
 3. The charge release circuit according to claim 2,wherein the second conductor comprises a plurality of gate lines, thefirst charge release unit comprises a plurality of first transistors,the first control line is perpendicular to the gate line, and theplurality of first transistors are in a one-to-one correspondence withthe plurality of gate lines; wherein a gate electrode of each of theplurality of first transistors is connected with the first control line,a first electrode of each of the plurality of first transistors isconnected with one gate line in the plurality of gate lines, and asecond electrode of each of the plurality of first transistors isconnected with the first conductor.
 4. The charge release circuitaccording to claim 2, wherein the second conductor comprises at leastone data line, the controller comprises a second control line, and thecharge release sub-circuit comprises a second charge release unit; andwherein the second charge release unit is respectively connected withthe at least one data line, the second control line and the firstconductor, and the second charge release unit is configured to conductthe first conductor and the at least one data line according to acontrol signal on the second control line.
 5. The charge release circuitaccording to claim 4, wherein the second conductor comprises a pluralityof data lines, the second charge release unit comprises a plurality ofsecond transistors, the second control line is perpendicular to the dataline, and the plurality of second transistors are in a one-to-onecorrespondence with the plurality of data lines; and wherein a gateelectrode of each of the plurality of second transistors is connectedwith the second control line, a first electrode of each of the pluralityof second transistors is connected with one data line in the pluralityof data lines, and a second electrode of each of the plurality of secondtransistors is connected with the first conductor.
 6. The charge releasecircuit according to claim 5, wherein the second conductor furthercomprises at least one pixel electrode, the controller further comprisesa third control line, and the charge release sub-circuit furthercomprises a third charge release unit, and wherein the third chargerelease unit is respectively connected with the gate line and the thirdcontrol line in the array substrate, and the third charge release unitis configured to write a control signal on the third control line intothe gate line so as to conduct each pixel electrode and the data lineconnected with the pixel electrode.
 7. The charge release circuitaccording to claim 6, wherein the third charge release unit comprises aplurality of third transistors, the plurality of third transistors arein a one-to-one correspondence with the plurality of gate lines in thearray substrate, and the second conductor comprises a plurality of pixelelectrodes connected with each gate line, and the third control line isperpendicular to the gate line, and wherein both a gate electrode and afirst electrode of each of the plurality of third transistors areconnected with the third control line, and a second electrode of each ofthe plurality of third transistors is connected with one gate line inthe plurality of gate lines.
 8. The charge release circuit according toclaim 1, wherein a volume of the first conductor is greater than that ofthe second conductor.
 9. The charge release circuit according to claim1, wherein the first conductor is a common electrode line or a storageelectrode line.
 10. A display substrate, comprising the charge releasecircuit according to claim
 1. 11. A display device, comprising a displaypanel, wherein the display panel comprises the display substrateaccording to claim
 10. 12. A charge release method of the display deviceaccording to claim 11, comprising: applying a control signal to thecontroller when the display panel is in a black-screen state, conductingthe first conductor and the second conductor under the control of thecontroller, and allowing charges on the second conductor to move to thefirst conductor.
 13. The method according to claim 12, wherein the firstconductor is a common electrode line or a storage electrode line, andthe second conductor is at least one of a gate line, a data line or apixel electrode.
 14. The method according to claim 12, wherein a volumeof the first conductor is greater than that of the second conductor. 15.The charge release circuit according to claim 3, wherein the secondconductor comprises at least one data line, the controller comprises asecond control line, and the charge release sub-circuit comprises asecond charge release unit; and wherein the second charge release unitis respectively connected with the at least one data line, the secondcontrol line and the first conductor, and the second charge release unitis configured to conduct the first conductor and the at least one dataline according to a control signal on the second control line.
 16. Thecharge release circuit according to claim 15, wherein the secondconductor comprises a plurality of data lines, the second charge releaseunit comprises a plurality of second transistors, the second controlline is perpendicular to the data line, and the plurality of secondtransistors are in a one-to-one correspondence with the plurality ofdata lines; and wherein a gate electrode of each of the plurality ofsecond transistors is connected with the second control line, a firstelectrode of each of the plurality of second transistors is connectedwith one data line in the plurality of data lines, and a secondelectrode of each of the plurality of second transistors is connectedwith the first conductor.
 17. The charge release circuit according toclaim 16, wherein the second conductor further comprises at least onepixel electrode, the controller further comprises a third control line,and the charge release sub-circuit further comprises a third chargerelease unit, and wherein the third charge release unit is respectivelyconnected with the gate line and the third control line in the arraysubstrate, and the third charge release unit is configured to write acontrol signal on the third control line into the gate line so as toconduct each pixel electrode and the data line connected with the pixelelectrode.
 18. The charge release circuit according to claim 17, whereinthe third charge release unit comprises a plurality of thirdtransistors, the plurality of third transistors are in a one-to-onecorrespondence with the plurality of gate lines in the array substrate,and the second conductor comprises a plurality of pixel electrodesconnected with each gate line, and the third control line isperpendicular to the gate line, and wherein both a gate electrode and afirst electrode of each of the plurality of third transistors areconnected with the third control line, and a second electrode of each ofthe plurality of third transistors is connected with one gate line inthe plurality of gate lines.
 19. The charge release circuit according toclaim 1, wherein a line width of the first conductor is greater thanthat of the second conductor.
 20. The charge release circuit accordingto claim 1, wherein the second conductor comprises at least one dataline, the controller comprises a second control line, and the chargerelease sub-circuit comprises a second charge release unit; and whereinthe second charge release unit is respectively connected with the atleast one data line, the second control line and the first conductor,and the second charge release unit is configured to conduct the firstconductor and the at least one data line according to a control signalon the second control line.